View W3EG6432S265D3_4590554.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

white electronic designs 1 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com preliminary* may 2005 rev. 6 w3eg6432s-d3 -jd3 features double-data-rate architecture ddr200, ddr266, ddr333 and ddr400 ? jedec design speci? cations bi-directional data strobes (dqs) differential clock inputs (ck & ck#) programmable read latency 2,2.5 (clock) programmable burst length (2,4,8) programmable burst type (sequential & interleave) edge aligned data output, center aligned data input. auto and self refresh serial presence detect power supply: ? v cc = v ccq = +2.5v 0.2v (100, 133 and 166mhz) ? v cc = v ccq = +2.6v 0.1v (200mhz) jedec standard 184 pin dimm package ? jd3 pcb height: 30.48 (1.20") max note: consult factory for availability of: ? lead-free products ? vendor source control option ? industrial temperature option description the w3eg6432s is a 32mx64 double data rate sdram memory module based on 256mb ddr sdram components. the module consists of eight 32mx8 ddr sdrams in 66 pin tsop packages mounted on a 184 pin fr4 substrate. synchronous design allows precise cycle control with the use of system clock. data i/o transactions are possible on both edges and burst lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. * this product is under development, is not quali? ed or characterized and is subject to change without notice. 256mb C 32mx64 ddr sdram unbuffered operating frequencies ddr400 @cl=3 ddr333 @cl=2.5 ddr266 @cl=2 ddr266 @cl=2 ddr266 @cl=2.5 ddr200 @cl=2 clock speed 200mhz 166mhz 133mhz 133mhz 133mhz 100mhz cl-t rcd -t rp 3-3-3 2.5-3-3 2-2-2 2-3-3 2.5-3-3 2-2-2
white electronic designs 2 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com may 2005 rev. 6 preliminary w3eg6432s-d3 -jd3 pin symbol pin symbol pin symbol pin symbol 1v ref 47 nc 93 v ss 139 v ss 2 dq0 48 a0 94 dq4 140 nc 3v ss 49 nc 95 dq5 141 a10 4 dq1 50 v ss 96 v ccq 142 nc 5 dqs0 51 nc 97 dqm0 143 v ccq 6 dq2 52 ba1 98 dq6 144 nc 7v cc 53 dq32 99 dq7 145 v ss 8dq354v ccq 100 v ss 146 dq36 9 nc 55 dq33 101 nc 147 dq37 10 nc 56 dqs4 102 nc 148 v cc 11 v ss 57 dq34 103 nc 149 dqm4 12 dq8 58 v ss 104 v ccq 150 dq38 13 dq9 59 ba0 105 dq12 151 dq39 14 dqs1 60 dq35 106 dq13 152 v ss 15 v ccq 61 dq40 107 dqm1 153 dq44 16 ck1 62 v ccq 108 v cc 154 ras# 17 ck1# 63 we# 109 dq14 155 dq45 18 v ss 64 dq41 110 dq15 156 v ccq 19 dq10 65 cas# 111 nc 157 cs0# 20 dq11 66 v ss 112 v ccq 158 nc 21 cke0 67 dqs5 113 nc 159 dqm5 22 v ccq 68 dq42 114 dq20 160 v ss 23 dq16 69 dq43 115 a12 161 dq46 24 dq17 70 v cc 116 v ss 162 dq47 25 dqs2 71 nc 117 dq21 163 nc 26 v ss 72 dq48 118 a11 164 v ccq 27 a9 73 dq49 119 dqm2 165 dq52 28 dq18 74 v ss 120 v cc 166 dq53 29 a7 75 ck2# 121 dq22 167 nc 30 v ccq 76 ck2 122 a8 168 v cc 31 dq19 77 v ccq 123 dq23 169 dqm6 32 a5 78 dqs6 124 v ss 170 dq54 33 dq24 79 dq50 125 a6 171 dq55 34 v ss 80 dq51 126 dq28 172 v ccq 35 dq25 81 v ss 127 dq29 173 nc 36 dqs3 82 v ccid 128 v ccq 174 dq60 37 a4 83 dq56 129 dqm3 175 dq61 38 v cc 84 dq57 130 a3 176 v ss 39 dq26 85 v cc 131 dq30 177 dqm7 40 dq27 86 dqs7 132 v ss 178 dq62 41 a2 87 dq58 133 dq31 179 dq63 42 v ss 88 dq59 134 nc 180 v ccq 43 a1 89 v ss 135 nc 181 sa0 44 nc 90 nc 136 v ccq 182 sa1 45 nc 91 sda 137 ck0 183 sa2 46 v cc 92 scl 138 ck0# 184 v ccspd pin configuration a0-a12 address input (multiplexed) ba0-ba1 bank select address dq0-dq63 data input/output dqs0-dqs7 data strobe input/output ck0, ck1, ck2 clock input ck0#, ck1#, ck2# clock input cke0 clock enable input cs0# chip select input ras# row address strobe cas# column address strobe we# write enable dqm0-dqm7 data-in-mask v cc power supply v ccq power supply for dqs v ss ground v ref power supply for reference v ccspd serial eeprom power supply sda serial data i/o scl serial clock sa0-sa2 address in eeprom v ccid v cc indenti? cation flag nc no connect pin names
white electronic designs 3 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com may 2005 rev. 6 preliminary w3eg6432s-d3 -jd3 functional block diagram cs0# dqs0 dqm0 dqs4 dqm4 dqs1 dqm1 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dm cs# dqs dqs2 dqm2 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dm cs# dqs dqs3 dqm3 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dm cs# dqs dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dm cs# dqs dqs5 dqm5 dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dm cs# dqs dqs6 dqm6 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dm cs# dqs dqs7 dqm7 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dm cs# dqs dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dm cs# dqs serial pd scl wp a0 a1 a2 sa0 sa1 sa2 sda ras# cas# ba0-ba1 we# a0-a12 cke0 ras#: ddr sdrams cas#: ddr sdrams ba0-ba1: ddr sdrams we#: ddr sdrams a0-a12: ddr sdrams cke0: ddr sdrams clock input 2 sdrams 3 sdrams 3 sdrams ck0, ck0# ck1, ck1# ck2, ck2# spd ddr sdrams ddr sdrams ddr sdrams ddr sdrams v ccspd v ccq v cc v ref v ss note: all datalines are terminated through a 22 ohm series resistor.
white electronic designs 4 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com may 2005 rev. 6 preliminary w3eg6432s-d3 -jd3 absolute maximum ratings parameter symbol value units voltage on any pin relative to v ss v in , v out -0.5 to 3.6 v voltage on v cc supply relative to v ss v cc , v ccq -1.0 to 3.6 v storage temperature t stg -55 to +150 c power dissipation p d 8w short circuit current i os 50 ma note: permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to recommended operating condition. exposure to higher than recommended voltage for extended periods of time could affect device reliability dc characteristics 0c t a 70c, v cc = v ccq = 2.5v 0.2v, v cc = v ccq = 2.6v 0.1v (200mhz) parameter symbol min max unit supply voltage v cc 2.3 2.7 v supply voltage v ccq 2.3 2.7 v reference voltage v ref 1.15 1.35 v termination voltage v tt 1.15 1.35 v input high voltage v ih v ref + 0.15 v ccq + 0.3 v input low voltage v il -0.3 v ref -0.15 v output high voltage v oh v tt + 0.76 v output low voltage v ol v tt -0.76 v capacitance t a = 25c, f = 1mhz, v cc = v ccq = 2.5v 0.2v, v cc = v ccq = 2.6v 0.1v (200mhz) parameter symbol max unit input capacitance (a0-a12) c in1 29 pf input capacitance (ras#,cas#,we#) c in2 29 pf input capacitance (cke0, cke1) c in3 29 pf input capacitance (ck0#,ck0) c in4 26 pf input capacitance (cs0#, cs1#) c in5 29 pf input capacitance (dqm0-dqm8) c in6 8pf input capacitance (ba0-ba1) c in7 29 pf data input/output capacitance (dq0-dq63)(dqs) c out 8pf
white electronic designs 5 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com may 2005 rev. 6 preliminary w3eg6432s-d3 -jd3 i dd specifications and test conditions 0c t a 70c, v cc = v ccq = 2.5v 0.2v, v cc = v ccq = 2.6v 0.1v (200mhz)v includes ddr sdram component only parameter symbol conditions ddr400@ cl=3 max ddr333@ cl=2.5-3-3 max ddr266@ cl=2 max ddr266@ cl=2.5 max ddr200@ cl=2 max units operating current i dd0 one device bank; active - precharge; t rc =t rc (min); t ck =t ck (min); dq,dm and dqs inputs changing once per clock cycle; address and control inputs changing once every two cycles. 1080 1000 1000 1000 1000 ma operating current i dd1 one device bank; active-read- precharge burst = 2; t rc =t rc (min); t ck =t ck (min); l out = 0ma; address and control inputs changing once per clock cycle. 1360 1360 1200 1200 1200 ma precharge power- down standby current i dd2p all device banks idle; power-down mode; t ck =t ck (min); cke=(low) 32 32 32 32 32 rna idle standby current i dd2f cs# = high; all device banks idle; t ck =t ck (min); cke = high; address and other control inputs changing once per clock cycle. v in = v ref for dq, dqs and dm. 480 400 360 360 360 ma active power-down standby current i dd3p one device bank active; power-down mode; t ck (min); cke=(low) 320 240 200 200 200 ma active standby current i dd3n cs# = high; cke = high; one device bank; active-precharge; t rc =t ras (max); t ck =t ck (min); dq, dm and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle. 560 480 400 400 400 ma operating current i dd4r burst = 2; reads; continuous burst; one device bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); l out = 0ma. 1600 1400 1200 1200 1200 ma operating current i dd4w burst = 2; writes; continuous burst; one device bank active; address and control inputs changing once per clock cycle; t ck =t ck (min); dq,dm and dqs inputs changing once per clock cycle. 1560 1400 1200 1200 1200 rna auto refresh current i dd5 t rc = t rc (min) 2080 2040 1880 1880 1880 ma self refresh current i dd6 cke 0.2v 32 32 32 32 32 ma operating current i dd7a four bank interleaving reads (bl=4) with auto precharge with t rc =t rc (min); t ck =t ck (min); address and control inputs change only during active read or write commands. 3760 3280 2800 2800 2800 ma
white electronic designs 6 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com may 2005 rev. 6 preliminary w3eg6432s-d3 -jd3 i dd1 : operating current : one bank 1. typical case : v cc =2.5v, t=25c 2. worst case : v cc =2.7v, t=10c 3. only one bank is accessed with t rc (min), burst mode, address and control inputs on nop edge are changing once per clock cycle. i out = 0ma 4. timing patterns : ? ddr200 (100 mhz, cl=2) : t ck= 10ns, cl2, bl=4, t rcd= 2*t ck , t ras= 5*t ck read : a0 n r0 n n p0 n a0 n - repeat the same timing with random address changing; 50% of data changing at every burst ? ddr266 (133mhz, cl=2.5) : t ck= 7.5ns, cl=2.5, bl=4, t rcd= 3*t ck , t rc= 9*t ck , t ras= 5*t ck read : a0 n n r0 n p0 n n n a0 n - repeat the same timing with random address changing; 50% of data changing at every burst ? ddr266 (133mhz, cl=2) : t ck =7.5ns, cl=2, bl=4, t rcd =3*t ck , t rc =9*t ck , t ras =5*t ck read : a0 n n r0 n p0 n n n a0 n - repeat the same timing with random address changing; 50% of data changing at every burst ? ddr333 (166mhz, cl=2.5) : t ck =6ns, bl=4, t rcd =10*t ck , t ras =7*t ck read : a0 n n r0 n p0 n n n a0 n - repeat the same timing with random address changing; 50% of data changing at every burst ? ddr400 (200mhz, cl=3) : t ck =5ns, bl=4, t rcd =15*t ck , t ras =7*t ck read : a0 n n r0 n p0 n n n a0 n - repeat the same timing with random address changing; 50% of data changing at every burst i dd7a : operating current : four banks 1. typical case : v cc =2.5v, t=25c 2. worst case : v cc =2.7v, t=10c 3. four banks are being interleaved with t rc (min), burst mode, address and control inputs on nop edge are not changing. iout=0ma 4. timing patterns : ? ddr200 (100 mhz, cl=2) : t ck =10ns, cl2, bl=4, t rrd =2*t ck , t rcd =3*t ck , read with autoprecharge read : a0 n a1 r0 a2 r1 a3 r2 a0 r3 a1 r0 - repeat the same timing with random address changing; 100% of data changing at every burst ? ddr266 (133mhz, cl=2.5) : t ck =7.5ns, cl=2.5, bl=4, t rrd =3*t ck , t rcd =3*t ck read with autoprecharge read : a0 n a1 r0 a2 r1 a3 r2 n r3 a0 n a1 r0 - repeat the same timing with random address changing; 100% of data changing at every burst ? ddr266 (133mhz, cl=2) : t ck =7.5ns, cl2=2, bl=4, t rrd =2*t ck , t rcd =2*t ck read : a0 n a1 r0 a2 r1 a3 r2 n r3 a0 n a1 r0 - repeat the same timing with random address changing; 100% of data changing at every burst ? ddr333 (166mhz, cl=2.5) : t ck =6ns, bl=4, t rrd =3*t ck , t rcd =3*t ck , read with autoprecharge read : a0 n a1 r0 a2 r1 a3 r2 n r3 a0 n a1 r0 - repeat the same timing with random address changing; 100% of data changing at every burst ? ddr400 (200mhz, cl=3) : t ck =5ns, bl=4, t rrd =10*t ck , t rcd =15*t ck , read with autoprecharge read : a0 n a1 r0 a2 r1 a3 r2 n r3 a0 n a1 r0 - repeat the same timing with random address changing; 100% of data changing at every burst detailed test conditions for ddr sdram i dd1 & i dd7a legend: a = activate, r = read, w = write, p = precharge, n = nop a (0-3) = activate bank 0-3 r (0-3) = read bank 0-3
white electronic designs 7 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com may 2005 rev. 6 preliminary w3eg6432s-d3 -jd3 ddr sdram component electrical characteristics and recommended ac operating conditions ac characteristics 403 335 262 263/265 202 parameter symbol min max min max min max min max min max units notes access window of dqs from ck/ck# t ac -0.7 +0.7 -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 -0.75 +0.75 ns ck high-level width t ch 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 t ck 26 ck low-level width t cl 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 t ck 26 clock cycle time cl = 3 tck (3) 5 7.5 ns 40, 45 cl = 2.5 t ck (2.5) 6 13 6 13 7.5 13 7.5 13 7.5 13 ns 40, 45 cl = 2 t ck (2) 7.5 13 7.5 13 7.5/10 13 7.5/10 13 7.5/10 13 ns 40, 45 dq and dm input hold time relative to dqs t dh 0.4 0.45 0.5 0.5 0.5 ns 23, 27 dq and dm input setup time relative to dqs t ds 0.4 0.45 0.5 0.5 0.5 ns 23, 27 dq and dm input pulse width (for each input) t dipw 1.75 1.75 1.75 1.75 1.75 ns 27 access window of dqs from ck/ck# t dqsck -0.60 +0.60 -0.60 +0.60 -0.75 +0.75 -0.75 +0.75 -0.75 +0.75 ns dqs input high pulse width t dqsh 0.35 0.35 0.35 0.35 0.35 t ck dqs input low pulse width t dqsl 0.35 0.35 0.35 0.35 0.35 t ck dqs-dq skew, dqs to last dq valid, per group, per access t dqsq 0.40 0.45 0.5 0.5 0.5 ns 22, 23 write command to ? rst dqs latching transition t dqss 0.72 1.28 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 t ck dqs falling edge to ck rising - setup time t dss 0.2 0.2 0.2 0.2 0.2 t ck dqs falling edge from ck rising - hold time t dsh 0.2 0.2 0.2 0.2 0.2 t ck half clock period t hp t ch, t cl t ch, t cl t ch, t cl t ch, t cl t ch, t cl ns 30 data-out high-impedance window from ck/ck# t hz +0.70 +0.70 +0.75 +0.75 +0.75 ns 16, 36 data-out low-impedance window from ck/ck# t lz -0.70 -0.70 -0.75 -0.75 -0.75 ns 16, 36 address and control input hold time (fast slew rate) t ihf 0.6 0.75 0.90 .90 .90 ns 12 address and control input setup time (fast slew rate) t isf 0.6 0.75 0.90 .90 .90 ns 12 address and control input hold time (slow slew rate) t ihs 0.6 0.80 1 1 1 ns 12
white electronic designs 8 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com may 2005 rev. 6 preliminary w3eg6432s-d3 -jd3 ddr sdram component electrical characteristics and recommended ac operating conditions (continued) ac characteristics 403 335 262 263/265 202 parameter symbol min max min max min max min max min max units notes address and control input setup time (slow slew rate) t iss 0.6 0.80 1 1 1 ns 12 address and control input pulse width (for each input) t ipw 2.2 2.2 2.2 2.2 2.2 ns load mode register command cycle time t mrd 10 12 15 15 15 ns dq-dqs hold, dqs to ? rst dq to go non-valid, per access t qh t hp - t qhs t hp - t qhs t hp - t qhs t hp - t qhs t hp - t qhs ns 22, 23 data hold skew factor t qhs 0.50 0.55 0.75 0.75 0.75 ns active to precharge command t ras 40 70,000 42 70,000 40 120,000 40 120,000 40 120,000 ns 31, 48 active to read with auto precharge command t rap 15 15 15 20 20 ns active to active/auto refresh command period t rc 55 60 60 65 65 ns auto refresh command period t rfc 70 72 75 75 75 ns 43 active to read or write delay t rcd 15 15 15 20 20 ns precharge command period t rp 15 15 15 20 20 ns dqs read preamble t rpre 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 t ck 37 dqs read postamble t rpst 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 t ck 37 active bank a to active bank b command t rrd 10 12 15 15 15 ns dqs write preamble t wpre 0.25 0.25 0.25 0.25 0.25 t ck dqs write preamble setup time t wpres 00000ns18, 19 dqs write postamble t wpst 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 t ck 17 write recovery time t wr 15 15 15 15 15 ns internal write to read command delay t wtr 21111t ck data valid output window na t qh - t dqsq t qh - t dqsq t qh - t dqsq t qh - t dqsq t qh - t dqsq ns 22 refresh to refresh command t refc 70.3 70.3 70.3 70.3 70.3 s 21 average periodic refresh interval t refi 7.8 7.8 7.8 7.8 7.8 s 21 terminating voltage delay to v cc t vtd 00000ns exit self refresh to non-read command t xsnr 70 75 75 75 75 ns exit self refresh to read command t xsrd 200 200 200 200 200 t ck
white electronic designs 9 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com may 2005 rev. 6 preliminary w3eg6432s-d3 -jd3 notes 1. all voltages referenced to v ss . 2. tests for ac timing, i dd , and electrical ac and dc characteristics may be conducted at nominal reference/supply voltage levels, but the related speci? cations and device operation are guaranteed for the full voltage range speci? ed. 3. outputs measured with equivalent load: output o u t p u t (v ( v out o u t ) reference r e f e r e n c e point p o i n t 50? 5 0 ? v tt t t 30pf 3 0 p f 4. ac timing and i dd tests may use a v il -to-v ih swing of up to 1.5v in the test environment, but input timing is still referenced to v ref (or to the crossing point for ck/ck#), and parameter speci? cations are guaranteed for the speci? ed ac input levels under normal use conditions. the mini-mum slew rate for the input signals used to test the device is 1v/ns in the range between v il (ac) and v ih (ac). 5. the ac and dc input level speci? cations are as de? ned in the sstl_2 standard (i.e., the receiver will effectively switch as a result of the signal crossing the ac input level, and will remain in that state as long as the signal does not ring back above [below] the dc input low [high] level). 6. v ref is expected to equal v ccq /2 of the transmitting device and to track variations in the dc level of the same. peak-to-peak noise (non-common mode) on v ref may not exceed 2 percent of the dc value. thus, from v ccq /2, v ref is allowed 25mv for dc error and an additional 25mv for ac noise. this measurement is to be taken at the nearest v ref bypass capacitor. 7. v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref and must track variations in the dc level of v ref . 8. i dd is dependent on output loading and cycle rates. speci? ed values are obtained with mini-mum cycle time at cl = 2 for 262, and 262, cl = 2.5 for 335 and 265, cl = for 403 with the outputs open. 9. enables on-chip refresh and address counters. 10. i dd speci? cations are tested after the device is properly initialized, and is averaged at the de? ned cycle rate. 11. this parameter is sampled. v cc = +2.5v 0.2v, v ccq = +2.5v 0.2v, v ref = v ss , f = 100 mhz, ta = 25c, v out (dc) = v ccq /2, v out (peak to peak) = 0.2v. dm input is grouped with i/o pins, re? ecting the fact that they are matched in loading. 12. for slew rates less than 1 v/ns and greater than or equal to 0.5 v/ns. if slew rate is less than 0.5 v/ns, timing must be derated: t is has an additional 50ps per each 100mv/ns reduction in slew rate from 500mv/ns, while t ih is unaffected. if slew rate exceeds 4.5v/ns, functionality is uncertain. 13. the ck/ck# input reference level (for timing referenced to ck/ck#) is the point at which ck and ck# cross; the input reference level for signals other than ck/ck# is v ref . 14. inputs are not recognized as valid until v ref stabilizes. exception: during the period before v ref stabilizes, cke < 0.3 x v ccq is recognized as low. 15. the output timing reference level, as measured at the timing reference point indicated in note 3, is v tt . 16. t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referenced to a speci? c voltage level, but specify when the device output is no longer driving (hz) or begins driving (lz). 17. the intent of the dont care state after completion of the postamble is the dqs- driven signal should either be high, low, or high-z and that any signal transition within the input switching region must follow valid input requirements. that is, if dqs transitions high [above v ihdc (min)] then it must not transition low (below v ihdc ) prior to t dqsh (min). 18. this is not a device limit. the device will operate with a negative value, but system performance could be degraded due to bus turnaround. 19. it is recommended that dqs be valid (high or low) on or before the write command. the case shown (dqs going from high-z to logic low) applies when no writes were previously in progress on the bus. if a previous write was in progress, dqs could be high during this time, depending on t dqss . 20. min (t rc or t rfc ) for i dd measurements is the smallest multiple of t ck that meets the minimum absolute value for the respective parameter. t ras (max) for i dd measurements is the largest multiple of t ck that meets the maximum absolute value for t ras . 21. the refresh period is 64ms. this equates to an average refresh rate of 7.8125s. however, an auto refresh command must be asserted at least once every 70.3s; burst refreshing or posting by the dram controller greater than eight refresh cycles is not allowed. 22. the valid data window is derived by achieving other speci? cations: t hp (t ck/2 ), t dqsq , and t qh (t qh = t hp - t qhs ). the data valid window derates directly porportional with the clock duty cycle and a practical data valid window can be derived. the clock is allowed a maximum duty cycle variation of 45/55, beyond which functionality is uncertain. 23. each byte lane has a corresponding dqs: x8 = dqs with dq0-dq7. 24. this limit is actually a nominal value and does not result in a fail value. cke is high during refresh command period (t rfc [min]) else cke is low (i.e., during standby). 25. to maintain a valid level, the transitioning edge of the input must: a. sustain a constant slew rate from the current ac level through to the target ac level, v il (ac) or v ih (ac). b. reach at least the target ac level. c. after the ac target level is reached, continue to maintain at least the target dc level, v il (dc) or v ih (dc). 26. jedec speci? es ck and ck# input slew rate must be 1v/ns (2v/ns if measured differentially). 27. dq and dm input slew rates must not deviate from dqs by more than 10 percent. if the dq/ dm/dqs slew rate is less than 0.5v/ns, timing must be derated: 50ps must be added to t ds and t dh for each 100mv/ns reduction in slew rate. if slew rate exceeds 4v/ns, functionality is uncertain. 28. v cc must not vary more than 4 percent if cke is not active while any bank is active. 29. the clock is allowed up to 150ps of jitter. each timing parameter is allowed to vary by the same amount. 30. t hp min is the lesser of t cl minimum and t ch minimum actually applied to the device ck and ck# inputs, collectively during bank active. 31. reads and writes with auto precharge are not allowed to be issued until t ras (min) can be satis? ed prior to the internal precharge command being issued. 32. any positive glitch in the nominal voltage must be less than 1/3 of the clock and not more than +400mv or 2.9v, whichever is less. any negative glitch must be less than 1/3 of the clock cycle and not exceed either 300mv or 2.2v, whichever is more positive. however, the dc average cannot be below 2.3v minimum.
white electronic designs 10 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com may 2005 rev. 6 preliminary w3eg6432s-d3 -jd3 33. the voltage levels used are derived from a mini-mum v cc level and the referenced test load. in practice, the voltage levels obtained from a properly terminated bus will provide signi? cantly different voltage values. 34. v ih overshoot: v ih (max) = v ccq + 1.5v for a pulse width 3ns and the pulse width can not be greater than 1/3 of the cycle rate. v il undershoot: v il (min) = -1.5v for a pulse width 3ns and the pulse width can not be greater than 1/3 of the cycle rate. 35. v cc and v ccq must track each other. 36. t hz (max) takes precedence over t dqsck (max) + t rpst (max) condition. t lz (min) will prevail over t dqsck (min) + t rpre (max) condition. 37. t rpst end point and t rpre begin point are not referenced to a speci? c voltage level but specify when the device output is no longer driving (t rpst ), or begins driving (t rpre ). 38. during initialization, v ccq , v tt , and v ref must be equal to or less than v cc + 0.3v. alternatively, v tt may be 1.35v maximum during power up, even if v cc / v ccq are 0v, provided a minimum of 42? of series resistance is used between the v tt supply and the input pin. 39. for 403, 335, 262, 263 and 265 speed grades, i dd3n is speci? ed to be 35ma per ddr sdram at 100 mhz. 40. the current part operates below the slowest jedec operating frequency of 83 mhz. as such, future die may not re? ect this option. 41. random addressing changing and 50 percent of data changing at every transfer. 42. random addressing changing and 100 percent of data changing at every transfer. 43. cke must be active (high) during the entire time a refresh command is executed. that is, from the time the auto refresh command is registered, cke must be active at each rising clock edge, until t ref has been satis? ed. 44. i dd2n speci? es the dq, dqs, and dm to be driven to a valid high or low logic level. i dd2q is similar to i dd2f except i dd2q speci? es the address and control inputs to remain stable. although i dd2f , i dd2n , and i dd2q are similar, i dd2f is worst case. 45. whenever the operating frequency is altered, not including jitter, the dll is required to be reset. this is followed by 200 clock cycles. 46. leakage number re? ects the worst case leakage possible through the module pin, not what each memory device contributes. 47. when an input signal is high or low, it is de? ned as a steady state logic high or logic low. 48. the 403 speed grade will operate with t ras (min) = 40ns and t ras (max) = 120,000ns at any slower frequency.
white electronic designs 11 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com may 2005 rev. 6 preliminary w3eg6432s-d3 -jd3 133.48 (5.255" max.) 3.99 (0.157 (2x)) 17.78 (0.700) 10.01 (0.394) 6.35 (0.250) 64.77 (2.550) 1.78 (0.070) 49.53 (1.950) 3.00 (0.118) (4x) 30.48 (1.20) max 2.31 (0.091) (2x) 1.27 (0.050 typ.) 6.35 (0.250) 128.95 (5.077") 131.34 (5.171") 2.54 (0.100 max) 3.99 (0.157) (min) 1.27 0.10 (0.050 0.004) package dimensions for jd3 * all dimensions are in millimeters and (inches) ordering information for jd3 part number speed cas latency t rcd t rp height* temperature w3eg6432s403jd3 200mhz/400mb/s 3 3 3 30.48 (1.20") 0c to 70c w3eg6432s335jd3 166mhz/333mb/s 2.5 3 3 30.48 (1.20") 0c to 70c w3eg6432s262jd3 133mhz/266mb/s 2 2 2 30.48 (1.20") 0c to 70c w3eg6432s263jd3 133mhz/266mb/s 2 3 3 30.48 (1.20") 0c to 70c w3eg6432s265jd3 133mhz/266mb/s 2.5 3 3 30.48 (1.20") 0c to 70c w3eg6432s202jd3 100mhz/200mb/s 2 2 2 30.48 (1.20") 0c to 70c note: 1 * consult factory for availability of lead-free products. (f = lead-free, g = rohs compliant) 2 * product speci? c part numbers are available for source control if needed, please consult factory for the correct part numbe r if a speci? c component vendor is preferred. 3 * consult factory for availability for industrial temperature (-40c to 85c) options
white electronic designs 12 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com may 2005 rev. 6 preliminary w3eg6432s-d3 -jd3 133.48 (5.255" max.) 3.99 (0.157 (2x)) 17.78 (0.700) 10.01 (0.394) 6.35 (0.250) 64.77 (2.550) 1.78 (0.070) 49.53 (1.950) 3.00 (0.118) (4x) 30.48 (1.20) max 2.31 (0.091) (2x) 1.27 (0.050 typ.) 6.35 (0.250) 128.95 (5.077") 131.34 (5.171") 2.54 (0.100 max) 3.99 (0.157) (min) 1.27 0.10 (0.050 0.004) package dimensions for d3 * all dimensions are in millimeters and (inches) ordering information for d3 part number speed cas latency t rcd t rp height* temperature w3eg6432s403d3 200mhz/400mb/s 3 3 3 30.48 (1.20") 0c to 70c w3eg6432s335d3 166mhz/333mb/s 2.5 3 3 30.48 (1.20") 0c to 70c w3eg6432s262d3 133mhz/266mb/s 2 2 2 30.48 (1.20") 0c to 70c w3eg6432s263d3 133mhz/266mb/s 2 3 3 30.48 (1.20") 0c to 70c W3EG6432S265D3 133mhz/266mb/s 2.5 3 3 30.48 (1.20") 0c to 70c w3eg6432s202d3 100mhz/200mb/s 2 2 2 30.48 (1.20") 0c to 70c note: 1 * consult factory for availability of lead-free products. (f = lead-free, g = rohs compliant) 2 * product speci? c part numbers are available for source control if needed, please consult factory for the correct part numbe r if a speci? c component vendor is preferred. 3 * consult factory for availability for industrial temperature (-40c to 85c) options
document title 256mb C 32mx64 ddr sdram unbuffered revision history rev # history release date status rev 0 initial release 3-18-02 advanced rev 1 added ddr333 1-30-03 advanced rev 2 2.1 added document title page 4-14-04 preliminary rev 3 removed "ed" from part number 8-04 preliminary rev 4 corrected "mo" device count 9-04 preliminary rev 5 5.1 added ddr400 5.2 added lead-free and rohs compliant notes. 12-04 preliminary rev 6 6.1 added jedec standard pcb 6.2 d3 option "not recommended for new designs" 5-05 preliminary white electronic designs 13 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com may 2005 rev. 6 preliminary w3eg6432s-d3 -jd3

▲Up To Search▲

Price & Availability of W3EG6432S265D3

	To Download W3EG6432S265D3 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .